1. Field of the Invention
This invention relates to arithmetic devices and more particularly to arithmetic devices used in support of digital signal processors.
2. Prior Art
In the prior art there exist arithmetic units which are utilized for digital processing; however, such prior art devices have substantial disadvantages as described herein below.
Firstly, prior art arithmetic units typically include a multiplier which is only capable of multiplying two signed numbers or two unsigned numbers. Such multiplying means are not capable of multiplying a signed number by an unsigned number.
Furthermore, the multiplier used in the prior art arithmetic units have a limited dynamic range. In particular, the dynamic range is typically from -1 to +1. As a result, the prior art arithmetic units are not capable of computing biquad IIR filter sections wherein the coefficient magnitudes are often greater than 1.
In addition, prior art arithmetic units are slow to indicate the existence of an overflow condition and typically perform all operations before indicating an overflow condition.